Worst Cases for the Exponential Function in the IEEE 754r decimal64 Format

Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND and OR gates. The proposed AND gate has no power supply, thus it can be referred as the Powerless AND gate. Similarly, the proposed two transistor OR gate has no ground and can be referred as Gr...

Partial Reversible Gates(PRG) for Reversible BCD Arithmetic

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Furthermore, in the recent years reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The major goal in reversible logic is to minimize t...

Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND & OR gates. The proposed AND gate has no power supply, thus it can be referred as the Powerless AND gate. Similarly, the proposed two transistor OR gate has no ground and can be referred as Grou...

Formal Correctness of Comparison Algorithms Between Binary64 and Decimal64 Floating-Point Numbers

We present a full Coq formalisation of the correctness of some comparison algorithms between binary64 and decimal64 floatingpoint numbers.

Software implementation of the IEEE 754R decimal floating-point arithmetic